(1) Field of the Invention
The present invention relates to semiconductor devices and more particularly to a method of forming a partially buried source in a split-gate flash memory cell in order to reduce the size of the cell and at the same time increase the coupling ratio for improved program speed.
(2) Description of the Related Art
Since the advent of the one-transistor memory cell, which contains one transistor and one capacitor, many variations of this simple cell have been advanced for the purposes of shrinking the size of the cell and, at the same time, improve its performance. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIG. 1. Here, a MOS transistor is formed on a semiconductor substrate (10) having a first doped region (20), a second doped region (30), a channel region (40), a gate oxide (50), a floating gate (60), intergate dielectric layer (70) and control gate (80). Substrate (10) and channel region (40) have a first conductivity type, and the first (20) and second (30) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in FIG. 1, the first doped region, (20), lies within the substrate. The second doped region, (30), lies within substrate (10) and is spaced apart form the first doped region (20). Channel region (40) lies within substrate (10) and between first (20) and second (30) doped regions. Gate oxide layer (50) overlies substrate (10). Floating gate (60), to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (50) while control gate (80), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (70) therebetween.
In the structure shown in FIG. 1, control gate (80) overlaps the channel region, (43), adjacent to channel (40) under the floating gate, (60). This structure is needed because when the cell is erased, it leaves a positive charge on the floating gate. As a result, the channel under the floating gate becomes inverted. The series MOS transistor (formed by the control gate over the channel region) is needed in order to prevent current flow from control gate to floating gate. The length of the transistor, that is the overlap of the control gate over the channel region (43) determines the cell performance. Furthermore, edges (61), (63) can affect the programming of the cell by the source size and hot electron injection through the intergate dielectric layer (70) at such edges. Hot electron injection is further affected by, what is called, gate bird's beak (67) that is formed in conventional cells. On the other hand, it will be known to those skilled in the art that corners such as (69) can affect the source coupling ratio also. Any such adverse effects attributable source size can be alleviated as disclosed later in the embodiments of this invention.
To program the transistor shown in FIG. 1, charge is transferred from substrate (10) through gate oxide (50) and is stored on floating gate (60) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed "on" of "off." "Reading" of the cell's state is accomplished by applying appropriate voltages to the cell source (20) and drain (30), and to control gate (80), and then sensing the amount of charge on floating gate (60). To erase the contents of the cell, the programming process is reversed, namely, charges are removed from the floating gate by transferring them back to the substrate through the gate oxide.
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim tunneling as is well known in prior art. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of Fowler-Nordheim tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, the floating gate can be erased by grounding the control gate and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate. Of importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Usually a thickness of between about 80 to 120 Angstroms is required to facilitate Fowler-Nordheim tunneling.
In the conventional memory cell shown in FIG. 1, word lines (not shown) are connected to control gate (80) of the MOS transistor, while the length of the MOS transistor itself is defined by the source (20) drain (30) N+ regions shown in the same Figure. As is well known by those skilled in the art, the transistor channel is defined by masking the N+ regions. However, the channel length of the transistor varies depending upon the alignment of the floating gate (60) with the source and drain regions. This introduces significant variations in cell performance from die to die and from wafer to wafer. Furthermore, the uncertainty in the final position of the N+ regions causes variations in the series resistance of the bit lines connected to those regions, and hence additional variation in the cell performance. Finally, in order to insure that the resistance of the bit line is acceptably low, the bit lines over the N+ regions are formed wider than the required minimum, thereby giving rise to an increase in the overall area of the cell. However, alternatively, the resistance of the bit line can be improved by judicious use of trenches without giving rise to an increase in the overall area of the cell as it is disclosed later in the embodiments of this invention.
In prior art, different methods are shown for fabricating different split-gate memory cells. A vertical channel device having buried source is described by Hsu in U.S. Pat. No. 5,627,393. In this approach, two levels of trenches are formed. The lower level trenches are etched through a well region into the buried source region and then filled with polysilicon to form gate electrodes. Drain regions are formed adjacent to the trenches by depositing, and etching back a second polysilicon layer and then ion implanting to form drain regions. Two sets of contact upper trenches are formed through silicon oxide layers subsequently deposited. The contact trenches are filled with tungsten to establish contact with drain and source regions.
Kim, in U.S. Pat. No. 5,527,727 discloses a method of manufacturing a split gate EEPROM cell where the electrical characteristics of the cell can be improved by decreasing the topology generated by the oxide film formed in a bit line containing a source region and a drain region. Hong, on the other hand, discloses a fieldless split-gate flash EPROM in U.S. Pat. No. 5,385,856. Guterman, et al., disclose still another EEPROM with split gate, in U.S. Pat. No. 5,313,421, utilizing source-side injection, allowing very small programming currents.
The present invention discloses a different method of fabricating a split-gate memory cell where the problems of programmability due to hot electron injection at edges of the cell and high resistance of lines as affected by the source size can be alleviated, and where the size of the cell can be reduced substantially.